CPLD vs. FPGA: Nine Key Differences You Should be Aware of
Most beginners, as well as experienced hardware designers, are familiar with the complexity of choice between CPLD and FPGA. Their features make them both suitable for a variety of projects. However, there is only one solution to be chosen in the long run. Today, we will take a look at the basics of these programmable devices and highlight their differences. Today, you will increase your awareness of the key differences and make a decision.
Introduction to the Basic Features of CPLD and FPGA
Programmable logic devices started a new age in the technology world many years ago. Since those times, hundreds of manufacturers and enthusiasts have been bringing value to the industry, designing new solutions, and offering devices of the highest quality possible.
Our journey through the CPLD vs. FPGA topic starts with selecting the best practical example. The Xilinx CoolRunner–II is one of the most popular CPLDs on the market. Its architecture is complex but rather clear. So almost everyone from a professional engineer to a student can understand the logic.
This type of device has a number of function blocks, ‘Function Block 1’ to ‘Function Block n.’ In our case, the number varies from 2 to 32. Each function block is connected to the Advanced Interconnect Matrix or AIM with 16 lines of output. In turn, 40 lines of input signal go from the AIM to the function blocks.
Each block includes 16 MacroCells, from MC1 to MC16. Each MacroCell consists of the following components:
- A flip-flop
- A Sum of Products PLA array.
Engineers use them for combinatorial or sequential design. There are 512 flip-flops available for use in our model.
These MacroCells have instant access to signals from the I/O Blocks. In our example, there are 16 signals.
The AIM of a CPLD is programmable. However, due to the device’s technical characteristics, the number of signals per block is limited.
The CPLD has a lot in common with its predecessor, the PLA. One of the common features is that each MacroCell is programmable thanks to the in-system programming interface. The connection is persistent: once the MacroCell is programmed, it remains the same for years. This is one of CPLD’s great advantages. In addition, the instant-on feature provides unique possibilities for users. The device starts working the moment it is powered up.
The interconnections provide access to hundreds of function logic blocks in CPLD. Now, let’s see what we have in FPGA.
There is no public access to newly-manufactured high-level FPGA schemes. So we will analyze the Xilinx documentation to clarify the picture of what is actually going on. (Read more:Great challenges FPGA prototyping must overcome)
The FPGA consists of millions of CLBs, or Configurable Logic Blocks, in a mass of programmable interconnects. Comparing the MacroCells to CLBs, we can say that CLBs are much more complex. Thus, they can fulfill complex logic tasks. What is the CLB made up of?
- Look-up tables
Some of the Xilinx devices may include over 3 billion flip-flops. And let’s go back to the CPLD chapter. There, all we had were just 512 flip-flops. In this case, the FPGA design is way more powerful.
Additionally, the FPGA includes many hardware components for performing the hardest tasks. It provides you with a great number of functions and choices as well as with a great flexibility thanks to the following components:
- Digital Signal Processing (DSP) blocks
- External memory controllers
- High-speed serial transceivers
- PLLs and MMCMs etc.
The important fact is that the FPGA architecture is based on look-up tables. The FPGA is blank when it powers up. A special element called the configuration circuit receives data from the ROM and configures the look-up tables. The configuration may take some time, so an FPGA doesn’t start to work instantly. The manufacturers are trying to solve this issue. Some of them have come up with a built-in configuration flash. Nevertheless, the setup time delays may still occur here. The reason is clear: the configuration data is based on the external ROM, not embedded in the scheme.
CPLD vs. FPGA: Nine Key Differences
Let’s consider the most important aspects of work from two different points of view – CPLD vs. FPGA: Who would win?
1. Starting the Work
The CPLD is on the moment you power up the device.
On the contrary, the FPGA needs some time to get up and running. It loads the configurations from the external ROM so the delay may take up to several dozen milliseconds.
The CPLD architecture is persistent. It remains programmed and set up even if the circuit is shut down.
The FPGA uses SRAM storage of configurations. So the memory is cleared immediately after the device is turned off.
3. Timing Analysis
The number of interconnects used by the CPLD is not so great. The architecture is simple, so timing analysis is fast and seamless.
FPGA logic is complex. It is rather heavy in comparison with CPLD. Signal routing is not determined, so timing analysis is harder. Some manufacturers provide implementation tools, so this can be fixed. But additional steps are required to improve this factor.
4. Logic Resources
The number of logic resources provided by CPLD is relatively small.
FPGA has myriad logic and storage elements. With them, you can design a really complex circuit.
The fabric scheme does not provide you with enough flexibility. Also, additional components for this purpose are not available.
With FPGA, you can use many other additional hardware components like blocks, controllers, transceivers, etc., which make the device highly flexible.
The built-in data storage makes the CPLD tools more secure.
The FPGA uses external memory so it is not as safe. There are solutions to handle this, for example:
- Data encryption
- Specific security extensions and approaches.
To modify the CPLD functionality, you need to turn off the device.
The FPGA does things differently. It works according to the Partial Reconfiguration method. You can change the circuit on the go: the system runs the design and updates it simultaneously. This feature is especially useful in accelerated programming.
8. Power Consumption
CPLD designs don’t require too much energy. For example, the newest solutions like CoolRunner-II need only 50 uA in ideal conditions.
On the other hand, we have FPGA which consumes much more energy.
The CPLD has a rather simple circuit. This is why they are quite cheap.
The FPGA provides more powerful functionality and performance, so the price may be higher.
As you can see, both devices have their pros and cons, strengths and weaknesses. But both fit particular project needs and find application in a variety of industries.
- Use CPLD for simple projects or in case your project requires the instant-on circuit.
- Go for FPGA in any other case.
- Use a combination of CPLD and FPGA for simple projects with controlling resets.
You need to have a clear vision of a project’s functionality to decide on the best option. And if you are still unsure about which device to choose, let us provide you with more detailed information and expert support.